 |
 |
 |
 |
 |
 |
 |
 |
 |
|
|
|
|
|
|
|
|
|
OpenAccess includes translators for reading and writing the standard formats that are commonly used in a design flow. All translators provide a full-featured, base implementation, which can be customized and extended through translator class inheritance. A direct interface to OpenAccess is always preferred, but translators provide an important interface to applications in a flow that do not provide a direct interface. Translators are also useful for validating the migration of applications to the OpenAccess database.
The following list provides links to the sections of this document that describe what is new or improved in the base translator implementations for this release.A new option for all translators is -DMSystem, which specifies which design management system to use for the library. An option that is common to all readers is -DMAttributes, which specifies one or more DM attributes to associate with each library that the translator creates.
The translators support LEF/DEF version 5.6 in addition to versions 5.3, 5.4, and 5.5. A new mode is added to the DEF reader to update a logical representation of a design with physical data. The GUI for these translators is removed, which eliminates the OpenAccess dependency on Qt.
def2oa has a new default mode that appends physical information to an oaDesign that already has a logical hierarchy. If the logical equivalent of a DEF net is not found by name, the translator searches for a logical net that connects to the same instTerm. def2oa skips any DEF components, pins, nets, and instance-terminals that are missing in the logical representation and issues a warning. If the oaDesign does not have a logical hierarchy, def2oa infers one from the hierarchical names. Certain physical-only objects, such as physical only pins, power/ground nets, globals, tie-hi/tie-low, and cover cells, are always created.
def2oa includes the -overwrite switch to disable this default behavior of appending physical information to an oaDesign.The LEF/DEF translators support version 5.6 syntax. The LEF 5.6 syntax highlights include:
For information about using the LEF translators and translation options, see the documentation for lef2oa and oa2lef.
The DEF 5.6 syntax highlights include:
For information about using the DEF translators and translation options, see the documentation for def2oa and oa2def.
Verilog is often an important source of front-end design data. The Verilog reader brings structural Verilog information into OpenAccess usually by using the embedded module hierarchy (EMH) to represent it. The writer generates structural Verilog preserving interfaces and multi-bit connectivity. It does not preserve behavioral constructs and original comments. In addition to the Verilog reader and writer, the verilogAnnotate translator is also provided.
The verilog2oa translator can create a module hierarchy in a single oaDesign or create a set of oaDesigns in OpenAccess. This translator supports mapping of global signals, tieHigh/tieLow nets, Verilog concatenations, net assignments, and forward references. verilog2oa stores port order information in OpenAccess.
verilog2oa provides several new options. The translator automatically finds the top module when used in default mode, but you can defeat the automatic top module detection and specify the module you want by using the -top module option. A -blackBox option creates a separate design for each empty Verilog module that has no instances and no assign statements.
oa2verilog supports mapping of global signals, tieHigh/tieLow nets, Verilog concatenations, and net assignments. The translator utilizes port ordering if available, or orders ports alphabetically when port ordering is not available.
The translator provides two new options. The -leafCell filename option directs oa2verilog to write stubs for leaf cells to the specified file instead of the file specified by the output option. The translator default behavior is to translate only the top module. The -recursive option directs the translator to recursively write all oaDesigns in the hierarchy that are in the same directory and have the same top view name.
The verilogAnnotate translator updates an existing OpenAccess design with information in a Verilog netlist. This translator updates an existing oaDesign with:
For additional information about Verilog translators, see the Verilog translator documentation.
SPEF represents both detailed and reduced model parasitic data for physical designs. spef2oa provides a source of data from parasitic extraction tools that do not provide a direct interface to OpenAccess. The SPEF reader and writer also provide a path between Cadence extraction engines and other analysis tools that lack a direct OpenAccess interface. The translators are also a means of comparing and validating the results of different extraction engines.
spef2oa annotates parasitic information onto an existing OpenAccess database that contains connectivity information. The translator can create either a single analysis point or three (min/typ/max) analysys points for a single oaDesign. spef2oa can read either detailed parasitics or reduced models. The default mode is to read both.
spef2oa uses the OpenAccess built in netwise loading capability for improved capacity. It supports the SPEF name map construct, and it handles split files by using a continuation syntax.
oa2spef reads parasitic data from the OpenAccess database, and writes SPEF. The translator can write a single analysis point or three (min/typ/max) analysis points for a single oaDesign. oa2spef writes nets with either detailed parasitics or reduced models. The default is to write both.
spef2oa uses the OpenAccess built in netwise loading capability for improved capacity. It writes a SPEF name map, and optionally writes SPEF in a compressed gzip format.
For additional information about the SPEF translators, see the documentation for spef2oa and oa2spef.
The GUI for these translators is removed, which eliminates the OpenAccess dependency on Qt.
Copyright © 2003-2010 Cadence Design Systems, Inc.
All rights reserved.