Keywords Not Allowed as Verilog Identifiers
| always |
end |
initial |
parameter |
small |
trior |
| and |
endattribute |
inout |
pmos |
specify |
trireg |
| assign |
endcase |
input |
posedge |
specparam |
use |
| attribute |
endmodule |
integer |
primitive |
strength |
vectored |
| begin |
endfunction |
join |
pull0 |
strong0 |
wait |
| buf |
endprimitive |
large |
pull1 |
strong1 |
wand |
| bufif0 |
endspecify |
macromodule |
pulldown |
supply0 |
weak0 |
| bufif1 |
endtable |
medium |
pullup |
supply1 |
weak1 |
| case |
endtask |
module |
rcmos |
table |
while |
| casex |
event |
nand |
reg |
task |
wire |
| casez |
for |
negedge |
release |
time |
wor |
| cmos |
force |
nmos |
repeat |
tran |
xnor |
| deassign |
forever |
nor |
rnmos |
tranif0 |
xor |
| default |
fork |
not |
rpmos |
tranif1 |
|
| defparam |
function |
notif0 |
rtran |
tri |
|
| disable |
highz0 |
notif1 |
rtranif0 |
tri0 |
|
| edge |
highz1 |
or |
rtranif1 |
tri1 |
|
| else |
if |
output |
scalared |
triand |
|
These keywords are legal if they are escaped. For example,
\module
is legal. Blanks or nonprinting characters are never allowed.
Return to top of page
Return to Programmers Guide topics
Copyright © 2001-2010 Cadence Design Systems, Inc.
All rights reserved.
