VHDL93 Keywords Not Allowed as VHDL Normal Identifiers

abs component guarded nor record then
access configuration if not register to
after constant impure null reject transport
alias disconnect in of rem type
all downto inertial on report unaffected
allow element inout open return units
and else is or rol until
architecture elseif label others ror use
array end library out select variable
assert entity linkage package severity wait
attribute exit literal port signal when
begin file loop postponed shared while
block for map private sla with
body function mod procedure sll xnor
buffer generate nand process sra xor
bus generic new pure srl  
case group next range subtype  




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