| Message Number |
|
Message Text |
| 40000 |
|
"%s", |
| 40001 |
|
"Unable to open file \"%s\"", |
| 40002 |
|
"Syntax Error: %s", |
| 40003 |
|
"Module \"%s\" is not the top module of design \"%s\"", |
| 40004 |
|
"Always blocks are not implemented", |
| 40005 |
|
"Binary operators are not implemented", |
| 40006 |
|
"Config declarations are not implemented", |
| 40007 |
|
"At least one element of a concatentation must be a string", |
| 40008 |
|
"Event declarations are not implemented", |
| 40009 |
|
"Function calls are not implemented", |
| 40010 |
|
"Function declarations are not implemented", |
| 40011 |
|
"Gate instantiations are not implemented", |
| 40012 |
|
"Generate blocks are not implemented", |
| 40013 |
|
"Genvar declarations are not implemented", |
| 40014 |
|
"Include statements are not implemented", |
| 40015 |
|
"Initial statements are not implemented", |
| 40017 |
|
"Integer arrays are not implemented", |
| 40018 |
|
"\"%s\" is not a valid instance name", |
| 40019 |
|
"Library text is not implemented", |
| 40020 |
|
"min:typ:max expressions always evaluate to \"typ\"", |
| 40021 |
|
"Multi-dimensional nets are not implemented", |
| 40022 |
|
"Multi-dimensional objects are not implemented", |
| 40023 |
|
"Multi-dimensional registers are not implemented", |
| 40024 |
|
"Negative values in ranges are not allowed", |
| 40025 |
|
"The IEEE 1364-2001 standard specifies that the expression following an \"if\" or \"while\" statement must be enclosed in parentheses", |
| 40026 |
|
"The size field of a number must be greater than zero", |
| 40027 |
|
"The specified number of bits is larger than the number of bits in an unsigned integer", |
| 40028 |
|
"\"x\" digits are not implemented", |
| 40029 |
|
"\"z\" digits are not implemented", |
| 40030 |
|
"Primitives are not implemented", |
| 40031 |
|
"Real declarations are not implemented", |
| 40032 |
|
"Realtime declarations are not implemented", |
| 40033 |
|
"Specparam statements are not implemented", |
| 40034 |
|
"Tasks are not implemented", |
| 40035 |
|
"Terminal \"%s\" was not found in module \"%s\"", |
| 40037 |
|
"Time declarations are not implemented", |
| 40038 |
|
"User defined primitives are not implemented", |
| 40039 |
|
"Unary operators are not implemented", |
| 40041 |
|
"Parameter arrays not implemented", |
| 40042 |
|
"Hierarchical names must be of the form \"module\".\"net\"", |
| 40043 |
|
"Module \"%s\" is not the module that contains global nets", |
| 40044 |
|
"Library \"%s\" was not found\n", |
| 40045 |
|
"Unresolved references exist for the following modules: %s", |
| 40046 |
|
"Terminal \"%s\" of module \"%s\" has position %d but the Verilog specification places it at position %d", |
| 40047 |
|
"The direction of terminal \"%s\" is not declared consistently", |
| 40049 |
|
"Inconsistent bit order for \"%s\"", |
| 40050 |
|
"Local declaration of the global net used for 1'b1 references, \"%s\"", |
| 40051 |
|
"Local declaration of the global net used for 1'b0 references, \"%s\"", |
| 40052 |
|
"The specified top module \"%s\" was not defined in the Verilog input", |
| 40053 |
|
"No master module for instances of \"%s\" the module will not be produced", |
| 40054 |
|
"Inconsistent width specified for terminal at position %d of module \"%s\"", |
| 40055 |
|
"Cell \"%s\" was not found in any library", |
| 40056 |
|
"Verilog module \"%s\" is represented by the top module of %s.%s.%s, \"%s\"", |
| 40057 |
|
"Design %s.%s.%s does not have a top module", |
| 40058 |
|
"Design %s.%s.%s exists. Cannot overwrite existing design data by default", |
| 40060 |
|
"\"%s\" is not a valid library name: %s", |
| 40061 |
|
"\"%s\" is not a valid view name: %s", |
| 40063 |
|
"Cannot convert floating point number \"%s\" to a binary number", |
| 40064 |
|
"No design instance with the name \"%s\" was found", |
| 40065 |
|
"The width of terminal \"%s\" does not match the width of net \"%s\". Some bits are unconnected.", |
| 40066 |
|
"The width of terminal \"%s\" does not match the width of net \"%s\".", |
| 40067 |
|
"The directions of the members of \"%s\" are not consistent", |
| 40068 |
|
"The top module is %s", |
| 40069 |
|
"Saving black box module %s as %s.%s.%s", |
| 40070 |
|
"Verilog module \"%s\" conflicts with leaf cellView %s.%s.%s. The leaf cellView will be instantiated instead of the Verilog module.", |
| 40071 |
|
"Module \"%s\" is not in the hierarchy of the top module \"%s\". It will be removed from the design.", |
