Public Methods | |
oaBitOrder (oaBitOrderEnum valueIn) | |
oaBitOrder (const oaString &name) | |
const oaString & | getName () const |
operator oaBitOrderEnum () const |
For example, A[9:1] and A[0:7] are both legal bus names. oaBitOrder provides information about whether the vector definition should be interpreted as A[9:0] or A[0:9]. The bit order of an explicit vector definition is independent of the order within individual objects with the same base name. For example, the bit order of an explicit oaBusNetDef is independent of the order within individual oaBusNets with the same base name. Verilog requires a single wire declaration for a given base name, and the range of that declaration covers all of the bit indices used by the sub-ranges that correspond to oaBusNets.
See Enum Wrappers in the Programmers Guide for a discussion of enum wrappers.
|
|
This function constructs an instance of an oaBitOrder object using the specified oaBitOrderEnum value. |
|
This function constructs an instance of an oaBitOrder object using the oaBitOrderEnum associated with the specified string name. This name must be defined in the legal set of names associated with oaBitOrderEnum.
|
|
This function returns the name string associated with the encapsulated oaBitOrderEnum value. |
|
This operator casts this oaBitOrder into its corresponding oaBitOrderEnum value. |
Copyright © 2002 - 2010 Cadence Design Systems, Inc.
All Rights Reserved.