OpenAccess to Verilog Translator (oa2verilog)

Overview

You can translate information from the OpenAccess database to Verilog using the oa2verilog command-line executable.

Command Syntax

Enter:

oa2verilog -lib library -cell cell -view view

Note: Currently, you must execute the oa2verilog command in the directory containing the library.

The oa2verilog command traverses all the modules in the input library, cell, and view and produces a Verilog netlist for each module. By default, the netlist is written to a file named after the input cell name in the current working directory. The translator creates a unique module definition for each pcell submaster, so that each instantiation of that submaster can reference the appropriate module definition.

See OpenAccess to Verilog Mapping for details about how OpenAccess database objects map to structural Verilog statements and constructs.

Use the -help or -h argument to display command-line help. The command-line arguments are described in the following table.

Required Arguments
-lib library	Specifies the input library name. For information about how the translator finds a library using the library definitions file, see How Translators Use Libraries.
-cell cell	Specifies the input cell name.
-verilog file	Specifies the name of the Verilog file to create. You can provide a filename or a file/path name.
-view view	Specifies the input view name.
Optional Arguments
-excludeLeaf	Specifies that leaf Verilog module definitions are not generated. This option cannot be used if the `leafFile` option is used. By default, `oa2verilog` outputs a Verilog module definition for each leaf cell.
-globals modName	Specifies the name of the module in which to define global nets, if any exist. The default is `globals`.
-help \| -h	Prints command-line help.
-leafFile fileName	By default, Verilog module definitions for leaf cells are written to the file specified with the `output` option. If you supply the `leafFile` option, the leaf module definitions are written to the given file name instead.
-libDefFile filename	Specifies the lib.defs file to load. The path to the lib.defs file can be a full or relative path. If this option is omitted, the default search mechanism of the DM system is used to find and load the lib.defs file.
-literal	Writes module interfaces literally. Using this option does not preserver the original interface.
-logFile file	Specifies the log filename. If this option is omitted, the log filename defaults to oa2verilog.
-noInfo msgIds	Suppresses the specified INFO messages. msgIds is a quoted, space separated list of numbers. Each number in the list represents the numerical portion of the ID for the message you want to suppress. None of the numbers in the list may be zero. Suppressed messages do not appear on the terminal or in the log file.
-noStopping	Writes module definitions for all module and design instance masters in the hierarchy. This option implies -recursive and cannot be used with -excludeLeaf or -leafFile.
-noWarning msgIds	Suppresses the specified WARNING messages. msgIds is a quoted, space separated list of numbers. Each number in the list represents the numerical portion of the ID for the message you want to suppress. None of the numbers in the list may be zero. Suppressed messages do not appear on the terminal or in the log file and are not included in the total of WARNING messages displayed in the summary. You can browse the list of error and warning messages to determine which you want to suppress.
-recursive	Writes a Verilog description of every module in the given design's module hierarchy and in the top level module of every instantiated design. By default, only the top module is translated.
-tieLow net	Specifies the name of the tie low net. The specified net must be a global net marked as either oacGroundSigType or oacTieLoSigType. The default tie low net name is tie0. An asterisk () may be specified instead of a net name. If an asterisk is specified, all global nets that are marked as oacTieLoSigType or as oacGroundSigType are mapped to 1'b0. Nets that are equivalent to the tie low net produce assign statements to `1'b0`. Instances with instTerms tied to one of these nets produce module instantiations with `1'b0` as the connecting net in the list of port connections. If a bus is tied to a bundle that is comprised of the tie low and tie high nets, the connection will be to a constant of the form `'b10001010011101...` where bundle members of the tie low net become zeros and bundle members of the tie high net become ones. For example, if net `"tie0,2tie1,tie0"` is connected to terminal `"a[3:0]"` of instance `"I1"`, the module instantiation in the output Verilog file is `"I1(.a('b0110)…)"`
-tieHigh net	Specifies the name of the tie high net. The specified net must be a global net marked as either oacPowerSigType or oacTieHiSigType. The default tie high net is tie1. An asterisk () can be specified instead of a net name. If an asterisk is specified, all global nets that are marked as oacTieHiSigType or oacPowerSigType are mapped to 1'b1. Nets that are equivalent to the tie high net produce assign statements to `1'b1`. Instances whose instTerms are tied to one of these nets produce module instantiations with `1'b1` as the connecting net in the list of port connections. If a bus is tied to a bundle that is comprised of the tie low and tie high nets, the connection will be to a constant of the form `'b10001010011101...` where bundle members of the tie low net become zeros and bundle members of the tie high net become ones. See tieLow net* above for an example.
-templateFile file	Specifies a file containing arguments to `oa2verilog`. You can specify a template file instead of entering a string of arguments on the command line. If you specify a template file, arguments on the command line have precedence over arguments specified in the file. So, if the same argument exists in the template file and in the command line, the translator uses the argument on the command line. Specify arguments in a template file as follows: Enter arguments in the template file without a dash (-) before the argument. Enter each argument and value pair on a single line. Separate the argument from its value using a space or a tab. Designate comment lines with a # sign as the first character in the line. Sample Template File # oa2verilog command line arguments logFile myoa2verilog.log libDefFile myLib.defs recursive
-v	Prints tool, format, and library version information.
-version	Prints tool and format version information.

Note: Command line arguments specifying library, cell, and view names are interpreted according to the Native name space. See Native Name Space in the Name Mapping article of the Programmers Guide for details about the native name space.

Handling Library Definitions File Errors

If your library definitions file has errors, or any of the referenced libraries cannot be opened, an error message is generated and translation is halted. If the library is not required to complete the translation, translation proceeds without an error or warning. For more information about this behavior, see the Handling Errors in lib.defs Files section in the Programmers Guide chapter How Translators Use Libraries.

Preserving the Semantic Direction of Assign Statements

oa2verilog attempts to preserve the semantic direction of assign statements beyond simple equivalency. For example, consider the following:

module test (output A, input B, output C, input D);
  assign A = B;
  assign C = D;
  assign A = C;
endmodule

To preserve the semantics of the Verilog, the translator groups the equivalent nets into driver and reciever sets according to the following rules:

If a net has an input term, it is in the driver set regardless of any other connections.
If a net does not have an input term but has an output instTerm, it is in the driver set.
In any other case, the net is in the reciever set.

oa2verilog generates assign statements that connect all drivers together followed by an assign statement that connects one driver to one reciever, where the reciever is on the left-hand-side. This is followed by assign statements that connect all the recievers together. Using the previous input Verilog example, oa2verilog generates:

module test (output A, input B, output C, input D);
  assign B = D;
  assign A = B;
  assign A = C;
endmodule

How the Translator Uses Namespaces

A namespace is a set of rules that define the legal characters and determine how names are interpretted. This translator uses the oaNative namespace to interpret library, cell, and view names in the command line. For example, to write a cell that will become the Verilog module with the escaped name \a/b use a command line with:

–cell a#2fb

Other names that refer to name-mapped OpenAccess objects, such as net and module names, use the Verilog namespace.

Error and Warning Message Format

Translators emit messages that report translation progress, report warnings about unusual data or conditions, or report problems with files or data that caused partial or complete translation failure. These messages are written to a log file so you can review translation status, identify error and warning conditions, and consider whether additional actions are needed.

OpenAccess translators use a standard message format to ensure comprehensive and consistent messaging. This message format consists of three elements, which are: message type keyword, message prefix, and message text.

In addition to the three standard elements, messages can also include two optional elements. An optional filename/line number element is included, when available, to more precisely identify the source of a problem or condition within the source data file. A context string is another optional element that is included, when available, to identify the type of data object that caused the message to be emitted. The following example shows a typical error message that includes the optional filename and line number element.

    ERROR: (OALEFDEF-50004): file.lef(123): A cell was not specified. Translation was terminated. 
    You must specify a cell.

One benefit of this message format is that it allows you to sort, filter, and examine only those types of messages that interest you. The keyword at the start of each message is either ERROR or WARNING and is always all uppercase. The message prefix identifies the translator family and the specific message source within the translator. The message prefix is a stable value that will not change between versions even when the message text gets updated. This makes it suitable for routine sorting and filtering.

If you seek assistance for resolving an issue related to a translator error or warning message, be sure to retain the message type keyword (ERROR or WARNING), and retain the message prefix to identify the translator family and the message source. Also make note of the filename/line number and context information if these are included in the message.

Return to top of page